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[SCM] oc8051

Description: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Platform: | Size: 1220608 | Author: 林建加 | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Platform: | Size: 9216 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] xsoc-beta-093

Description: This free cpu-ip! use verilog
Platform: | Size: 3341312 | Author: 王军 | Hits:

[Other] jtag_verilog

Description: verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
Platform: | Size: 6144 | Author: 陈俊 | Hits:

[Other Embeded program] ethernet.tar

Description: 以太网10/100M IP核Verilog源码，可综合。-IP Ethernet 10/100 nuclear Verilog source can be integrated.
Platform: | Size: 934912 | Author: 箫勇天 | Hits:

[VHDL-FPGA-Verilog] 8051IPcore，verilogHDL实现

Description: 用verilog写的很好的cpu core-using Verilog write a good cpu core
Platform: | Size: 52224 | Author: 刘烨波 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 70656 | Author: lile | Hits:

[Software Engineering] m16550a_verilog_rtl

Description: mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
Platform: | Size: 25600 | Author: cray | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] my_ip_core

Description: 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
Platform: | Size: 51200 | Author: 刘海 | Hits:

[VHDL-FPGA-Verilog] fft_IPcore

Description: 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
Platform: | Size: 8719360 | Author: 李杰 | Hits:

[VHDL-FPGA-Verilog] CAN_IPCore

Description: CAN_IPCore CAN协议的IP核源代码 verilog 语言
Platform: | Size: 61440 | Author: maliang | Hits:

[Other Embeded program] ip

Description: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Platform: | Size: 5391360 | Author: 钟阳 | Hits:

[SCM] 32-bit_RISC_IP_Core

Description: 32位RISC单片机verilog源码内包含说明文档经过他人测试通过-32-bit RISC single-chip Verilog source code contains documentation of others after the test
Platform: | Size: 33792 | Author: 栾日超 | Hits:

[VHDL-FPGA-Verilog] Ethernet_verilog_ip_core

Description: Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。-Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful.
Platform: | Size: 903168 | Author: houlongting | Hits:

[VHDL-FPGA-Verilog] i2c_p_altera

Description: altera i2c slave ip核verilog 编写-altera i2c slave ip to prepare nuclear Verilog
Platform: | Size: 1583104 | Author: 1984taozi | Hits:

[Other] EHERNETIPcore

Description: 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
Platform: | Size: 69632 | Author: season | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: | Size: 11264 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] pipelined_fft_64

Description: 利用IP Core编写的Verilog程序，实现FFT变换，希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
Platform: | Size: 99328 | Author: chengyungang | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:
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